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Modelling of HVDC converters for real-time transient simulators

University of British Columbia

This thesis presents developments in the computer modelling of High Voltage Direct Current (HVDC) converters and other FACTS devices for EMTP-type simulators. The high number and frequency of switching operations in power electronic converters cause numerical difficulties that require additional computational effort. The additional computational burden requires the development of techniques that can accelerate the simulation speeds of conventional electromagnetic transient modelling and may allow real-time simulations. The main results are two models that effectively reduce the computational time required to obtain the solution of an electrical network containing HVDC converters. Both approaches have in common the principle of subdividing an electrical circuit containing a 6«-valve converter into at least n subsystems. For each 6-valve subsystem, the 64 matrix combinations are precalculated and prestored in computer memory. The interaction between subsystems to obtain the network solution is particular to each approach. With this criterion, the number of precalculated combinations for a 24-valve HVDC substation is reduced from more than 16 million to only 256. Both models present a considerable reduction in the computational time required to simulate circuits containing HVDC converters. The most efficient model has been successfully implemented in the real time power systems simulator under development by the power research group at the University of British Columbia. The exact calculation of the network solution at switching events is another important aspect required to accurately simulate power electronic converters in power systems. The thesis proposes the zero crossing detection algorithm, which eliminates the erroneous delays present in traditional EMTP simulators. The proposed algorithm resynchronizes the solution to the original simulation time increment. To solve the problem originated by the forced commutation of Gate Turn Off Thyristors, an exploratory solution technique is proposed. This methodology eliminates the unrealistic voltage spikes that arise when chopping currents in discrete-time simulators. The resultant algorithm avoids the necessity of forcing the semiconductors to work as pairs, as some EMTP simulators solve the problem. Finally, the thesis includes a model for a Thyristor Controlled Reactor that maintains a constant conductance at switching operations, thus reducing the computational time when modelling Static Var Compensator substations.

Thesis/Dissertation

application/pdf

2009-07-03

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http://hdl.handle.net/2429/10168

Electrical and Computer Engineering

University of British Columbia

UBCV

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