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Delay compensated fade prediction based CDMA closed loop power control

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Title: Delay compensated fade prediction based CDMA closed loop power control
Author: Lee, Peter Ming Wong
Degree: Master of Applied Science - MASc
Program: Electrical and Computer Engineering
Copyright Date: 2004
Issue Date: 2009-11-24
Series/Report no. UBC Retrospective Theses Digitization Project [http://www.library.ubc.ca/archives/retro_theses/]
Abstract: Power control is essential in Code Division Multiple Access (CDMA) systems in order to reduce the near-far effect, optimize,the system capacity, and combat the signal degradation due to fading. One problem with Closed Loop Power Control (CLPC) is the delay introduced by power measurement and round-trip delay in the power control loop. We study the impact of power control loop delays on Frame Error Rate (FER) performance under a range of channel conditions. A new CLPC algorithm with delay compensation and fade prediction is then proposed to mitigate the effects of loop delays on CLPC. Delay compensation can reduce power oscillation amplitude around the desired received power level and fade prediction can forecast an upcoming fade in order to mitigate its effect. The FER performance on the forward link of an Interim Standard - 2000 (IS-2000) CDMA system using the delay compensated fade prediction based CLPC algorithm is studied. Simulations with a detailed IS-2000 physical layer model and various Third Generation Partnership Project 2 (3GPP2) channel models are used to illustrate the performance gains of the proposed CLPC algorithm over the conventional CLPC algorithm. The performance of the proposed CLPC algorithm as a function of mobile speed, delay, and carrier frequency is analyzed. It is found that the proposed CLPC algorithm performs better than the conventional CLPC algorithm by about 1 dB for a range of mobile speeds of interest. The performance improvement obtainable by using the proposed CLPC algorithm can reduce the interference and result in an increase in the system capacity. Finally, the effect of power control bit (PCB) errors on the performance of the proposed CLPC algorithm is studied. Simulation results indicate that the proposed CLPC algorithm is still beneficial when the PCB error rate is 5%.
Affiliation: Applied Science, Faculty of
URI: http://hdl.handle.net/2429/15640
Scholarly Level: Graduate

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