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Gallium arsenide integrated circuit modeling, layout and fabrication

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Title: Gallium arsenide integrated circuit modeling, layout and fabrication
Author: Rutherford, William C.
Degree Master of Applied Science - MASc
Program Electrical and Computer Engineering
Copyright Date: 1987
Subject Keywords Metal semiconductor field-effect transistors; Gallium arsenide semiconductors
Abstract: The object of the work described in this thesis was to develop GaAs integrated circuit modeling techniques based on a modified version of SPICE 2, then layout, fabricate, model and test ion implanted GaAs MESFET integrated sample and hold circuits. A large signal GaAs MESFET model was used in SPICE to evaluate the relative performance of inverted common drain logic (ICDL) digital integrated circuits compared to other circuit configurations. The integrated sample and hold subsequently referred to as an integrated sampling amplifier block(ISAB), uses a MESFET switch with either one or two guard gates to suppress strobe feedthrough. Performance guidelines suggested by the project sponsor indicate an optimal switch sampling pulse width capability of 25 ps with 5 ps rise and fall time. Guard gates are included in the switch layout to evaluate pulse feedthrough minimization. The project sponsor suggested -20 dB pulse feedthrough isolation and minimum sampling switch off isolation of -20 dB at 10 GHz as project guidelines. Simulations indicate that a 0.5 µm gate length process approaches the suggested performance guidelines. A mask layout was designed and modeled including both selective implant and refractory self aligned gate processes. The refractory self aligned gate process plasma etched t-gate structure produces a sub 0.5 µm gate length.
URI: http://hdl.handle.net/2429/26733
Series/Report no. UBC Retrospective Theses Digitization Project [http://www.library.ubc.ca/archives/retro_theses/]
Scholarly Level: Graduate

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