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A bounded delay simulator

University of British Columbia

Detecting the presence of timing problems in digital circuits is a difficult matter, but one that can be greatly simplified with the aid of effective analysis tools. Such tools have traditionally lacked the ability to detect the presence of race and hazard conditions. In this thesis we present a simulation tool that is able to detect such problems. In addition, the tool provides two mechanisms for doing so. One approach gives the user the capability of explicitly generating all possible states of the circuit in response to an input change. This type of analysis is extremely time consuming but describes all behaviours possible according to the underlying model. The other approach is far more computationally efficient, dealing mainly with computing the final outcome. Alternatively, this second approach enables the user to analyse a circuit using "symbolic data". However, it is somewhat pessimistic, giving rise to "false negative" results at times. Together though, the two approaches form a useful workbench for verification of circuit designs.

Thesis/Dissertation

application/pdf

2008-12-18

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http://hdl.handle.net/2429/3137

Computer Science

University of British Columbia

UBCV

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