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An integrated low-cost functional tester for CMOS logic

University of British Columbia

This thesis focuses on improving the quality of tests performed by low-cost testers for Very Large Scale Integration (VLSI) chips. The testing of timing parameters become increasingly important with higher performance technology. Circuits that operate correctly at low speeds may fail at higher speeds because of timing problems. Most low-end test systems lack the performance required to conduct the timing diagnostics needed to perform more advanced testing of modern VLSI chips. Areas of improvement in low-cost test systems include increasing vector memory, test speed, or I/O timing and wave formatting capability. Increasing I/O timing and wave formatting capability provides a good compromise of improved tester functionality at a reasonable cost. These features provide considerably more improvements in test quality than simply increasing the raw test speed (or test pattern rate). A test strategy was developed that exploits this improved timing and I/O waveform for matting capability to generate short high-speed clock bursts which can be used to perform testing at speeds equivalent to a much higher rate than the tester’s pattern rate. This strategy can be used to test many digital designs. However, using this strategy for “high-speed” testing requires more effort in test pattern development and more test vectors than an equivalent test performed on a high-speed tester. This approach can also be used in existing high-end testers that already have the required timing and waveform formatting capabilities. A functional tester system for CMOS logic was developed that provides these improved timing and I/O formatting features. This system integrates most of tester circuits into modular functional tester chips (FTCs) which are used in parallel to form a tester. Vector encoding combined with an internal lookup table was used to reduce the memory bandwidth required to support the increased functionality. A single-channel FTC was designed and implemented on a 3.8mm x 2.9mm die and requires only 40-pins which gives considerable allowance for future increases in memory width and channels. Measurements from earlier prototypes of the FTC waveform formatter give worst case timing resolutions of 1ns and maximum rise-fall skews of 1.2ns. Worst case skews between devices were on the order of 1ns. These results are very reasonable considering the relatively conservative standard cell design using 1.2m CMOS.

Thesis/Dissertation

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2009-02-23

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http://hdl.handle.net/2429/4946

Electrical and Computer Engineering

University of British Columbia

UBCV

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