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Performance evaluation of hybrid buffer ATM switch

University of British Columbia

Buffer management and cell scheduling are the most important factors affecting the design of packet switching architectures for ATM networks. Buffering is the major resource that dominates both the cost and performance of ATM switch fabrics. Buffer management is required whenever the instantaneous cell arrival rate at a switch output is higher than the output link rate. This thesis presents a hybrid buffer ATM switch architecture in which the buffer management scheme is realized by dedicated output buffers and a shared buffer. A new approach based on queue tail management, as well as distributed priority scheduling is incorporated in the proposed switch design. The proposed scheme aims at enhancing the performance of ATM switches by maintaining the head cells of logical output queues in relatively short dedicated output buffers, while maintaining the long tails of overflowing queues in a shared pool managed by a more intelligent buffer management unit. Under this scheme higher priority (or delay-sensitive) cells can be forwarded immediately to the output buffers potentially blocking some lower priority (but loss-sensitive) cells from advancing into the output buffers. If the shared buffer is full, then a suitable push-out scheme is employed. The output buffers employ a distributed priority scheduling technique for sending cells to output links. The proposed scheme is capable of handling multipriority traffic and of satisfying the QoS requirements of each class using a very simple architectural scheme with simplified distributed control policies compared to other schemes previously proposed. The hybrid buffer switch performance is evaluated using discrete time queueing theory and using simulation. We provide detailed analysis of the buffer management scheme by decomposing the complex partial sharing buffer analysis into an equivalent queueing problem. The thesis provides semi-closed form expressions for various performance measures. The discrete time queueing model is verified by simulation. The computation complexity of the queueing model is much smaller than that of similar models in the literature. The switch performance under multi-class traffic is critical to the network operation because real-time and non-real-time traffic demands different "quality of service" (QOS) regarding delay jitter and cell loss rate. For efficient buffer management, a simple two-class priority scheme is implemented in the output buffers to minimize cell delay and delay jitter for the delaysensitive (or real-time) traffic. A simulation package is developed and applied to evaluate the hybrid buffering switch under two-class (loss-sensitive and delay-sensitive) traffic using two different hybrid scheduling and buffer management polices. The extensive simulation results indicate that the QoS requirements for both traffic classes can be easily met by appropriately dimensioning the hybrid priority scheduling and buffer management policies. The hybrid distributed buffer control provides for flexible scheduling and keeps the hardware implementation cost lower than other switch architectures.

Thesis/Dissertation

application/pdf

2009-03-09

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http://hdl.handle.net/2429/5807

Electrical and Computer Engineering

University of British Columbia

UBCV

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