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Built-in jitter test schemes for mixed-signal integrated circuits

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Title: Built-in jitter test schemes for mixed-signal integrated circuits
Author: Dalmia, Kamal
Degree Master of Applied Science - MASc
Program Electrical and Computer Engineering
Copyright Date: 1996
Abstract: Recent years have seen an unparalleled growth in the speed and complexity of VLSI circuits. Analog and mixed-signal circuits are going through a resurgence and continue to pose new challenges to VLSI test engineers. The state-of-the-art in the mixed-signal and analog test domain is to use application-specific test methodologies to tackle individual problems. The same is true for testing the high-speed clock signals used in present day integrated circuits (ICs) for their analog attributes. Jitter is one of the ways of quantifying the accuracy of a clock signal. Present day digital automatic test equipment (ATE) does not possess enough resolution to be suitable for jitter tests of high-speed clock signals such as SONET's (Synchronous Optical Network) 155.52 MHz and 622.08 MHz. In this thesis, the jitter test problem of high-speed clocks is approached with a built-in self-test (BIST) perspective. A BIST scheme is presented for the jitter tolerance test of clock and data recovery units typically found in data transceiver ICs. A cost-effective scheme based on the utilization of existing components for test purposes is presented. Some possible variations of the presented scheme are discussed. A second BIST scheme, focused on jitter testing of clock signals in a sampling-based digital signal processing (DSP) environment, is presented. Again, the focus is on the re-use of typically existing blocks on such ICs.
URI: http://hdl.handle.net/2429/7771
Series/Report no. UBC Retrospective Theses Digitization Project [http://www.library.ubc.ca/archives/retro_theses/]
Scholarly Level: Graduate

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