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The buffered fat tree switch for ATM networks

University of British Columbia

The development of ATM (Asynchronous Transfer Mode) switches is one of the main tasks required to implement B-ISDN (Broadband Integrated Services Data Networks). This thesis proposes a general class of scalable ATM switches based on buffered tree structures. A distinguishing feature of the proposed switch is that it has been designed to handle nonuniform as well as uniform traffics robustly while fully utilizing switch resources (buffers and bandwidth). The buffer-size and bandwidth of each stage of the switch are specified by parameters which can be computed to optimize the switch with respect to cost, utilization, cell loss and total delay. The thesis also develops a discrete-time approximation model for analyzing the performance of the proposed switch. In particular, the analysis determines the influence of various design parameters on optimizing the switch performance. Similar to pure output buffered switches with fully interconnected fabrics, the BFT switch can easily achieve a throughput of 100 percent at much less complexity. Analysis show that delay and cell loss probability of the switch can be greatly enhanced by applying cut-through routing. They also show that more buffers are required by the lower stages of the switch to achieve a desired cell loss probability and this reduces coupling of input traffics. Simulation was used to further study the behavior of the buffers in the switch under uniform and bursty traffics. Keywords: ATM, switch architecture, performance analysis, tree-based switches.

Thesis/Dissertation

application/pdf

2009-05-23

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http://hdl.handle.net/2429/8100

Electrical and Computer Engineering

University of British Columbia

UBCV

DSpace