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UBC Theses and Dissertations
Testing for floating gates defects in CMOS circuits Rafiq, Sumbal
Abstract
This thesis studies the detectability of MOS floating gate transistor faults considering classical Static Voltage, Dynamic Voltage and Static Current testing strategies. The behavior of the defect depends on two classes of parameters: the predictable and unpredictable parameters. A floating gate fault can induce abnormal logic values, additional delays, or increased power supply current. Consequently, classical test strategies can only detect floating gate faults for a given range of the unpredictable parameter. Here, a new test scheme is proposed, which allows a considerable current to flow in the faulty logic gate in stable state, making the circuit with a floating gate IDDQ testable. It is shown that a combination of voltage and current testing can ensure complete detection of the floating gate defects, i.e., regardless of the unpredictable parameters. Analysis with increasing initial charge on the floating gate transistor shows how the detectability intervals become smaller for the voltage testing strategies and increase for the static current strategy. Keywords: Floating gate testing, IDDQ testing, gate opens, floating gate defect model.
Item Metadata
Title |
Testing for floating gates defects in CMOS circuits
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Creator | |
Publisher |
University of British Columbia
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Date Issued |
1998
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Description |
This thesis studies the detectability of MOS floating gate transistor faults considering
classical Static Voltage, Dynamic Voltage and Static Current testing strategies. The
behavior of the defect depends on two classes of parameters: the predictable and
unpredictable parameters. A floating gate fault can induce abnormal logic values,
additional delays, or increased power supply current. Consequently, classical test
strategies can only detect floating gate faults for a given range of the unpredictable
parameter. Here, a new test scheme is proposed, which allows a considerable current to
flow in the faulty logic gate in stable state, making the circuit with a floating gate IDDQ
testable. It is shown that a combination of voltage and current testing can ensure
complete detection of the floating gate defects, i.e., regardless of the unpredictable
parameters. Analysis with increasing initial charge on the floating gate transistor shows
how the detectability intervals become smaller for the voltage testing strategies and
increase for the static current strategy.
Keywords: Floating gate testing, IDDQ testing, gate opens, floating gate defect model.
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Extent |
3159851 bytes
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Genre | |
Type | |
File Format |
application/pdf
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Language |
eng
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Date Available |
2009-05-26
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Provider |
Vancouver : University of British Columbia Library
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Rights |
For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use.
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DOI |
10.14288/1.0065086
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URI | |
Degree | |
Program | |
Affiliation | |
Degree Grantor |
University of British Columbia
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Graduation Date |
1998-11
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Campus | |
Scholarly Level |
Graduate
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Aggregated Source Repository |
DSpace
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Item Media
Item Citations and Data
Rights
For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use.