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Safety verification conditions for software-intensive critical systems

University of British Columbia

This dissertation proposes an approach to generating "safety verification conditions" (SVCs) that improves upon the accuracy and thoroughness of approaches that rely primarily on engineering judgment. This approach, "Verification Tree Method" (VTM), is part of an overall system safety engineering process intended to eliminate or mitigate hazards in the development of a software-intensive critical system. VTM carried out to the level of a "black box" view of the system results in a set of system safety requirements. VTM can also be used to derive SVCs at the software component and the source code levels. The SVCs can then be used as input into the corresponding level of testing. VTM is based on Fault Tree Analysis (FTA). Like FTA, VTM involves tracing a given hazard is traced backwards through the system to cover all the ways in which a hazard can occur. VTM enhances FTA with a constrained syntax and "proof-by-contradiction" style reasoning to support the systematic derivation of SVCs. The SVCs include key safety-related temporal relationships. The result of the analysis is a rigorous safety argument that provides greater confidence that the SVCs, if satisfied, will be sufficient to mitigate the hazard. This informal argument can be validated with a formal verification technique. VTM is illustrated in this dissertation with a (hypothetical) chemical factory information system.

Thesis/Dissertation

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2009-05-28

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http://hdl.handle.net/2429/8371

Computer Science

University of British Columbia

UBCV

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